1. Field of the Invention
The invention generally relates to memory controllers utilized in computer systems, and more particularly, a single memory controller utilizing a plurality of input frequencies.
2. Description of the Related Art
The technology and capabilities of personal computer systems have generally been advancing at a fast pace for a number of years. However, the actual advancement of capabilities has not necessarily been uniform. For example, the capabilities and speeds of the microprocessor, the foundation of the personal computer, have dramatically increased in the last several years and appear to be continuing to increase at this high rate. On the other hand, a similar advancement curve has not been shown in memory devices, particularly in the effective speeds of memory devices, so that the disparity between the microprocessor speeds and the memory speeds has gotten larger. Further, other portions of the external constraints on a personal computer may also limit advancement in certain areas. For example, in many cases bus specifications were designed and developed for a particular time period, but as time progressed, devices which were much more powerful were developed. However, if those powerful devices were to be used in an interchangeable bus, such as one according to the ISA or Industry Standard Architecture, then some of the improvements could not be used and so designs can be standardized at lesser performance levels because of other limitations in the system.
One solution that has developed to these problems is the modular personal computer. In those designs many of the elements are located on interchangeable cards. For example, in most modular computers the processor system is located on an interchangeable card which can be readily replaced to allow the use of different microprocessors. Not only can types of microprocessors change but additionally so can the speeds of a particular microprocessor. For example, in many lines the Intel Corporation (Intel) 80386SX chip forms the low end either at 16 or 20 MHz versions, with a steady progression up through the compatible lines leading up to and ultimately concluding with 33 MHz or even 50 MHz 80486 microprocessors from Intel. By simply interchanging the processor card, the remaining components of the computer system can be reused and the theoretical cost of the performance increase is reduced.
However, there are certain disadvantages to this modular design. The most common disadvantage relates to the operation of the memory systems. In most high performance personal computers the memory is located on a bus which is tightly coupled to the processor and preferably is 32 bytes wide. The input/output (I/O) bus, such as the ISA or Extended Industry Standard Architecture (EISA) bus is wholly separate from this tightly coupled, proprietary bus. More details on the EISA bus are available in Appendix 1 in application Ser. No. 431,741, filed Nov. 3, 1989, which is hereby incorporated by reference. The I/O bus is effectively constrained because of the standardization that has developed over the years, but it is satisfactory for this portion of the system to remain relatively static because optimizations can be developed on the proprietary bus. Therefore, the main memory is located on this proprietary bus, called the host bus in some cases.
Because of the great differences in speeds and addressing techniques of the microprocessors used in modular systems, actual access to the memory devices varies greatly between the various microprocessors. However, the memory is located over a shared bus, so that in many cases the memory interface is fixed at a single variation, which is optimal for only one particular microprocessor and reduces performance in all other cases. Therefore, depending upon the configuration of the computer system, overall system performance can often be increased only at levels much less than that theoretically possible based on just the change of capabilities from one microprocessor to another. The memory interface becomes a limiting factor, particularly as clock rates of the microprocessor change.
If the memory controller is located on the common system board used in modular designs or on the memory board itself, then it has been common that these particular limitation problems would automatically develop, because memory controllers are typically only single clock speed based devices. If the memory controller is actually located and interchangeable along with the processor card, then performance can be improved when the processor card is changed, but the design costs are increased because of the need to design a memory controller for each particular microprocessor. In addition, production volumes of the particular memory controller component would be reduced as compared to the situation where it was installed on the system board or on the memory board. Therefore, there are significant cost burdens when a memory controller is interchangeable with the processor card. A tradeoff must be made at design time between cost and performance, i.e. using a single memory controller for all systems or changing the memory controller with the processor card.